The present invention relates to the structure of a semiconductor device and a method of manufacturing the same and, more particularly, to an element structure of a Metal Insulator-Semiconductor Field Effect Transistor (to be referred to as a MISFET hereinafter) which is excellent in a high-speed operation and a method of manufacturing the same.
As conventional semiconductor devices using MISFETs, memory devices such as dynamic RAMs or static RAMs formed on silicon substrates, processors using CMOS logic circuits, and the like are mass-produced.
In order to improve the integration density or performance of such a semiconductor device, miniaturization of a MISFET serving as a component is a necessary condition, and development of miniaturization technique and necessity of a short-channel effect and parasitic resistance suppression of the MISFET increase together with transition of generation of a semiconductor device.
As a method of suppressing a short-channel effect, for example, a Lightly Doped Drain structure (to be referred to as an LDD structure hereinafter) shown in FIG. 1 is known. In a MISFET having the LDD structure, a polysilicon gate 4 is formed on a semiconductor substrate through a gate oxide film 3, and ion implantation is performed by using the polysilicon gate 4 as a mask, so that shallow impurity diffusion layers 5 are formed on both the sides of the polysilicon gate 4 to be adjacent to a channel region formed at the gate electrode 4. In addition, gate sidewall spacers 6 are formed on the source/drain sides of the polysilicon gate 4, and ion implantation is performed by using the gate sidewall spacers 6 and the polysilicon gate 4 as masks, so that deep impurity diffusion layers are formed.
Since the impurity diffusion layers are used as source/drain regions 7 for supplying a drive current of a MISFET, voltage drop is increased by the resistances in the impurity diffusion layers. For this reason, the impurity concentration of this portion must be as high as possible. In order to form a diffusion layer having a high impurity concentration by ion implantation, an amount of implanted impurity per unit area (to be referred to a dose amount hereinafter) must be increased, and an acceleration voltage of ion implantation must be increased.
When the acceleration voltage of impurity ions is increased, the depth of ion implantation increased. For this reason, deep impurity diffusion layers are generally formed in the source/drain regions 7. When a gate length decreases with miniaturization of the MISFET, the decrease in distance between the source/drain regions adversely affects the threshold voltage of the MISFET and considerably degrades cut-off characteristics of the MISFET.
In order to activate the ion-implanted impurity, a high-temperature heat treatment must be performed. However, at this time, since the impurity is also laterally diffused, the distance between the source/drain regions in which the impurity is deeply implanted more decreases, and it is difficult to suppress the off-leakage current. The changes in characteristics with miniaturization of the MISFET are generally called a short-channel effect.
In order to reduce the short-channel effect in the LDD structure, shallow diffusion layers are formed to be adjacent to both the sides of the polysilicon gate 4, and the off-leakage current is suppressed such that the distance between the deep diffused layers of the source/drain regions 7 is as large as possible even if the length of the polysilicon gate 4 decreases. Shallow diffusion layers 5 shown in FIG. 1 are called source/drain extension regions.
In order to reduce the resistances of the source/drain regions 7 and the resistance of the polysilicon gate 4, as shown in FIG. 1, a low-resistance layer constituted by a silicide of high melting point metal 8 is formed on the source/drain regions 7 and the polysilicon gate 4. Since the silicide of high melting point metal 8 is formed in a self-aligned manner, the structure of the high-speed MISFET is called as a SALICIDE (abbreviation of self-aligned silicide) structure.
In order to improve the performance of the MISFET in a deep submicron region, a gate length must be decreased, and the dimension of depth must also be scaled down in proportion. Therefore, when the short-channel effect is to be reduced in the LDD structure, the shallow extension regions 5 must be formed, and at the same time, the source/drain regions 7 must be made shallow. However, since in general, high impurity concentration layer can not be made shallow, the shallowness of the ion implantation is limited to a predetermined level.
In the SALICIDE structure, as indicated by a broken-line circle in FIG. 1, the junction of the extension region 5 becomes close to the end portion of the silicide layer 8 on the drain side, and the formation of the silicide layer 8 on the drain region tend to cause increase a leakage current of a drain junction. The increase in leakage current especially poses a problems at the drain junction to which a large voltage is applied in operation of the MISFET. When an integrated circuit having a high integration level is constituted by CMOS circuits of low power dissipation, it is a necessary condition to remove the leakage current of constituent MISFETs.
In order to avoid the problem of the above LDD structure, an elevated source/drain structure shown in FIG. 2 is proposed. In this structure, silicon epitaxial layers 51 are grown on source/drain regions, and ions are implanted into source/drain diffusion layers by using gate sidewall spacers 6 and a polysilicon gate 4 as masks. At this time, since the ion implantation is performed through silicon epitaxial layers 51, the depth of the source/drain regions 7 from the interface of epitaxial layer and silicon substrate 1 is small to suppress a short-channel effect.
However, in the elevated source/drain structure, selective epitaxial growth of silicon at a high temperature of 800xc2x0 C. or higher is additionally performed, and the number of processing steps increases. At the same time, extra diffusion of impurity implanted in a channel region for threshold voltage control and in the extension regions is advanced. Therefore, this technique cannot always obtain a preferable result as a production technique for a deep submicron region.
Therefore, a means for realizing the structure of a new MISFET having the same advantages as those of an elevated source/drain structure without high-temperature heat treatment processing is strongly demanded.
As shown in FIG. 2, in the elevated source/drain structure, when the silicon epitaxial layers 51 are formed on a silicon substrate having (100) surface, (311) facets are easily generated opposite to the polysilicon gate 4, and parasitic capacitance is formed between the silicide layer 8 and the polysilicon gate 4. The gate-drain parasitic capacitance disadvantageously degrades the high frequency performance. Here, the facet indicates a small crystal surface having a special crystal orientation.
As another structure for suppressing a short-channel effect, a UMOS structure (to be described below) is known. That is, as shown in FIG. 3, a U-shaped deep trench is formed in a semiconductor substrate 1, source/drain regions 62 and extension regions 61 are formed on the surface of the silicon substrate.
In this UMOS structure, a channel region and a gate insulating film 3 are formed on the inner surface of a deep trench, and a gate electrode 63 is formed to bury the trench. Since source/drain regions 7 have no surfaces which are opposed to each other inside the semiconductor substrate 1 in the structure, the structure is excellent to avoid a short-channel effect. However, since the gate electrode 63 is adjacent to the source/drain regions 62 through the thin gate insulating film 3, a large gate/drain parasitic capacitance is formed to disadvantageously degrade the high frequency performance of the MISFET.
As described above, in a conventional MISFET in a deep submicron region, when the source/drain regions are to be made shallow to suppress the short-channel effect, a high-concentration impurity diffusion layer required to reduce a series resistance cannot be obtained. In addition, the source/drain regions are to be made effectively shallow by using the elevated source/drain structure, high-temperature heat treatment processing such as a silicon epitaxial processing step is required, and a gate-drain parasitic capacitance is excessively large in the UMOS structure to disadvantageously degrade the high frequency performance.
The present invention has been made to solve the above problems, and has as its object to realize a new MISFET structure which can suppress a short-channel effect in a deep submicron region without additional high temperature processing and has excellent high frequency performance.
A semiconductor device and a method of manufacturing the same according to the present invention provide the structure of a high performance MISFET which has source/drain regions having a diffusion layer depth being sufficient to prevent generation of a leakage current at a drain junction in a SALICIDE process and which suppresses a short-channel effect and a method of manufacturing the structure. It is another object to provide the structure of a high performance MISFET having performance being more excellent than that of an elevated source/drain structure and a method of manufacturing the structure.
More specifically, there is provided a semiconductor device having a MIS-type field effect transistor comprising a concave formed in at least a semiconductor substrate, a channel region formed on a bottom surface of the concave, source/drain extension regions connected to both ends of the channel region and formed on the bottom surface of the concave, and source/drain regions being close to or adjacent to side surfaces of the concave, formed along a surface of the semiconductor substrate in a direction of depth, and connected to the source/drain extension regions, wherein side surfaces of the concave on a source/drain side constitute a rounded surface.
Preferably, the concave is constituted by a trench formed from the surface of the semiconductor substrate in the direction of depth.
According to the present invention, there is provided a semiconductor device having a MIS-type field effect transistor comprising a concave constituted by a trench formed in a semiconductor substrate, a channel region formed on a bottom surface of the concave, source/drain extension regions connected to both ends of the channel region and formed on the bottom surface of the concave, and source/drain regions formed on a surface of the semiconductor substrate being close to or adjacent to side surfaces of the concave and connected to the source/drain extension regions.
Preferably, a position where an impurity concentration of the source/drain regions in the direction of depth is maximum almost coincides with a position where an impurity concentration of the source/drain extension regions in the direction of depth is maximum at a connecting portion.
More preferably, a taper angle set to upwardly increase the opening portion is given to the concave.
More preferably, the concave comprises a gate formed on the bottom surface of the concave through a gate insulating film, and gate sidewall spacers consisting of an insulator formed on side surfaces of the gate, and the gate sidewall spacers are formed to partially cover the side surfaces of the concave extending on at least the source/drain side of the gate.
More preferably, the gate sidewall spacers are formed to entirely cover the side surfaces of the concave extending on at least the source/drain side of the gate.
More preferably, ion implantation for threshold voltage control of the MIS-type field effect transistor is performed to only the bottom surface of the concave.
According to the present invention, there is provided a method of manufacturing a semiconductor device comprising the steps of forming an etching mask constituted by a first insulating film having an opening portion including a gate forming portion and source/drain extension regions forming portion on a semiconductor substrate, forming a trench in the semiconductor substrate in correspondence with the opening portion of the etching mask, forming a gate insulating film constituted by a second insulating film on an inner surface of the trench, forming a gate material film on the second insulating film, patterning the gate material film to form a gate on a central portion between both sides of the trench on a source/drain side through the second insulating film, implanting impurity ions into at least a bottom surface of the trench by using the gate as a mask to form source/drain extension regions, forming a third insulating film to cover a surface of the semiconductor substrate subjected to the steps, forming gate sidewall spacers constituted by the third insulating film by using anisotropic etching to cover the inner surface of the trench extending on the source/drain side of the gate, and implanting impurity ions into the source/drain regions by using the gate having the gate sidewall spacers as a mask to form a MIS-type field effect transistor having source/drain regions being close to or adjacent to side surfaces of the trench of the semiconductor substrate and connected to the source/drain extension regions on the bottom surface of the trench.
According to the present invention, there is provided a method of manufacturing a semiconductor device comprising the steps of forming an etching mask constituted by a first insulating film including a gate forming portion and source/drain extension regions forming portion and having an opening portion formed therein on a semiconductor substrate, forming a trench in the semiconductor substrate in correspondence with the opening portion of the etching mask, forming a gate insulating film constituted by a second insulating film on an inner surface of the trench, forming a gate material film to cover the surface of the semiconductor substrate subjected to the above steps, further forming a third insulating film on the gate material film, etching-back the upper surfaces of the third insulating film and the gate material film to form a gate forming etching mask constituted by the third insulating film buried in the gate material film on a central portion between both sides of the mask opening portion on the source/drain side, and anisotropically etching the gate material film by using the third insulating film buried in the gate material film as a mask to process the gate, thereby forming a MIS-type field effect transistor having a self-aligned gate formed on a central portion between both sides of the trench on the source/drain side.
Preferably, when a gate length of the MIS-type field effect transistor is represented by L, a length of the opening portion, in a direction of the gate length, of the opening portion of the etching mask constituted by the first insulating film is represented by LW, and the thickness of the gate material film is represented by d, a relationship Lxe2x89xa6LWxe2x88x922d is satisfied.
According to the present invention, there is provided a method of manufacturing a semiconductor device comprising, forming an etching mask constituted by a first insulating film including a gate forming portion and source/drain extension regions forming portion and having an opening portion formed therein on a semiconductor substrate, forming a trench in the semiconductor substrate in correspondence with the opening portion of the etching mask, forming a gate insulating film constituted by a second insulating film on an inner surface of the trench, forming a third insulating film to cover the surface of the semiconductor substrate subjected to the above steps, forming sidewall spacers constituted by the third insulating film by using anisotropic etching on side surfaces of the mask opening on a source/drain side, forming a gate material film to cover the surface of the semiconductor substrate subjected to the above steps, etching-back the upper surfaces of the third insulating film and the gate material film to form a gate constituted by the gate material film buried between the sidewall spacers on a central portion between both sides of the mask opening portion on the source/drain side, and selectively removing the first and third insulating films to form a MIS-type field effect transistor having a self-aligned gate formed on a central portion between both sides of the trench on the source/drain side.
Preferably, the trench is formed by isotropic etching such that the side surfaces of the trench on the source/drain side constitute a rounded surface.
More preferably, ion implantation for threshold voltage control of the MIS-type field effect transistor is performed to only the bottom surface of the trench.
More preferably, the first, second, and third insulating films are an SiO2 film formed by an LPCVD (low pressure chemical vapor deposition) method using TEOS (tetraethylorthosilicate), an SiO2 film formed by thermal oxidation of silicon, and an SiN film formed by a CVD method, respectively. The first insulating film is formed to be stacked on a thermal oxidation film formed as a buffer layer on the semiconductor substrate.
More preferably, according to the present invention, there is provided a method of manufacturing a semiconductor device further comprising the steps of implanting impurity ions into at least the bottom surface of the trench by using the self-aligned gate as a mask to form source/drain extension regions, forming a fourth insulating film to cover the surface of the semiconductor substrate subjected to the steps, forming gate sidewall spacers constituted by the fourth insulating film by using anisotropic etching to cover the inner surface of the trench extending on the source/drain side of the gate, and implanting impurity ions into the source/drain regions by using the gate having the gate sidewall spacers as a mask to form source/drain regions being close to or adjacent to side surfaces of the trench of the semiconductor substrate and connected to the source/drain extension regions on the bottom surface of the trench.
More preferably, there is provided a method of manufacturing a semiconductor device further comprising the step of, after a silicide film of high melting point metal is formed on a silicon surface exposed to the source/drain regions and upper surfaces of the gate consisting of polysilicon by forming a high melting point metal film to cover the surface of the semiconductor substrate and performing heat treatment, removing the high melting point metal film remaining on the gate sidewall spacers.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.